Integrated circuit chips are typically manufactured by forming the active devices for many chips on a single wafer of semiconductor material. The wafer is metallized to form the required interconnections among the active devices. The wafer is then diced into individual chips. The chips are mounted on a next level of packaging such as a printed circuit board, a multilayer ceramic (MLC) substrate, or other substrate, to form a single chip or multi-chip module.
Microelectronic systems have required ever increasing density of input/output (I/O) connections between an integrated circuit chip and its next level packaging. Accordingly, the art has increasingly turned to an interconnection technology which uses solder bumps or solder balls to electrically and mechanically connect the chip I/O pads to pads on a next level of packaging. This interconnection technology is also known as "controlled collapse chip connections" ("C-4") or "flip chip" technology. This technology has also been used in environments which do not require high I/O densities.
Many techniques have been heretofore described for forming solder bumps on an integrated circuit chip. For example, U.S. Pat. No. 4,950,623 to Dishon entitled Method of Building Solder Bumps, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference, describes a method of forming a solder bump on an underbump metallurgy by depositing a layer of solder-soluble metal on the underbump metallurgy so as to cover the underbump metallurgy. A layer of solidified solder is then coated on the solder soluble metal. The solder is then heated until the layer of solder melts and the solder-soluble metal dissolves in the melted solder. The surface tension of the melted solder draws the solder and dissolves soluble metal away from the nonwettable passivation layer which surrounds the underbump metallurgy, to form a spheroidal solder bump.
Another solder bump fabrication technique is described in Japanese Patent No. 55-111127 by Saga et al., published on Aug. 27, 1980 and entitled Method of Building Solder Bumps. This patent describes a two-step melting process for forming solder bumps. In a first low temperature heating step, an under-bump metallurgy layer is dissolved. Then, the photoresist which was used to define the underbump metallurgy is removed and the chip is tested in an unspecified manner. Then, a high temperature heating step is performed to form a hemispherical solder bump.
Other techniques for forming solder bumps involve transfer from a decal chip onto a device chip or a multilayer ceramic structure. See, for example, IBM Technical Disclosure Bulletins Vol. 22, No.3, page 996, August 1979 entitled Decaled Solder Transfer; Vol. 21, No.12, May 1979 page 4835 entitled Solder Rework Technique; Vol.21, No.12, May 1979 page 4834 entitled Solder Volume Optimization; and Vol. 22, No. 3, August 1979, page 995 entitled Method to Change Solder Composition of Chip.
In the manufacture of chips, some testing is typically performed at the wafer level. However, it is difficult to perform exhaustive tests of the chips at the wafer level. Similarly, some tests are performed at the module level after the chip is incorporated into the next level package. However, detection of failure at this level often requires scrapping the entire package or may require expensive rework of the package. Accordingly, it is highly desirable to perform testing of the chip after it has been diced from the wafer but before it is mounted on a next level package. Testing, as used herein, includes any and all operations, electrical or otherwise, which are typically performed on integrated circuits. Examples of such operations include parametric measurements, verification of functionality, erasure of Erasable Programmable Read-Only Memories (EPROM), programming of Programmable Logic Devices (PLDS) and power-on burn-in. Similarly, it is highly desirable to perform a "burn-in" at elevated temperatures (e.g. 160.degree. C.) and for long times (e.g. hundreds of hours) to identify early failures.
Unfortunately, it is difficult to perform "burn-in and test" on chips having solder bumps thereon. These chips are difficult to probe due to the very high density and close spacing of the solder bumps. Moreover, if the solder bumps are probed and simultaneously burned-in, distortion and squashing of the solder bumps typically occurs, which renders the chips unusable or requires expensive rework. Chip burn-in may also damage the next level package.
Techniques have recently been developed to allow test and burn-in of C-4 chips. For example, U.S. Pat. Nos. 5,006,792 and 5,073,117 both to Malhi et al. and both entitled Flip-Chip Test Socket Adaptor and Method, describe a test socket which includes a plurality of cantilever beams for making electrical contact to a bare chip. The cantilevers are designed to deflect and compensate for variations in solder bumps on the bare chips. Unfortunately, since solder bump connections typically are formed in an array over the entire face of an integrated circuit chip, it is difficult to form cantilever beam connections to all of the solder bumps. Moreover, these beams may squash the solder bumps during burn-in and test.
Another electrical connector for contacting C-4 chips during burn-in and test is described in U.S. Pat. No. 4,975,079 to Beaman et al. entitled Connector Assembly for Chip Testing. The connector includes a plurality of rigid conductors embedded therein, and a concave opening aligned with an end of each conductor so that each concave opening exposes the conductor and mates with the contact areas on the chip. Unfortunately, such a connector may also unduly stress the solder balls during burn-in and test.
Another technique for burn-in and test of C-4 chips is described in U.S. Pat. No. 5,065,227 to Frankeny et al. entitled Integrated Circuit Packaging Using Flexible Substrate. An integrated circuit chip having solder balls thereon is mounted on a substrate having input/output lines which extend outward from the integrated circuit footprint to an area on the substrate which is accessible. The integrated circuit chip can thereby be tested prior to mounting on its ultimate carrier. Once tested, the chip and the substrate are excised from the roll of substrate material. This excised, pretested package, which includes both the chip and the flexible substrate, can be mounted directly onto the ultimate carrier. Unfortunately, the flexible substrate is an additional package level which may impact the reliability of the overall package, and limits the density and performance attainable.
Finally, another technique for testing C-4 chips is described in U.S. Pat. No. 5,007,163 to Pope et al. entitled Non-Destructure (sic) Method of Performing Electrical Burn-In Testing of Semiconductor Chips. An electrically conductive, liquid eutectic joint is formed at room temperature with low pressure between electrical terminals on a chip and a circuitized substrate. The eutectic joint remains liquid at test temperatures, while enabling test completion. At the end thereof, chips and pads are separated and any eutectic material residue thereon is removed. Unfortunately, the liquid burn-in/test interconnections may be unreliable and the liquid eutectic joint may be unstable. Moreover, the liquid eutectic may alloy with the solder bumps and thus may be difficult to remove.
As the above survey indicates, the art has heretofore not developed a satisfactory method for performing "burn-in and test" of C-4 chips.